Call for Papers

The submission deadline has passed


HCPM 2017 welcomes submissions of research as well as position papers. Please find important information below:


Workshop Goals

HPCM aims to discuss potential strategies, opportunities, and challenges for supercomputing beyond the scaling limits of Moore’s Law. Due to the multidisciplinary nature of this problem, formulating a strategy is likely to require a comprehensive re-thinking of technologies, ranging from innovative materials and devices, circuits, system architectures, programming systems, system software, and applications. HPCM will feature paper presentations, keynote addresses, and short panels to foster foster interdisciplinary dialog across the necessary spectrum of stakeholders: applications, algorithms, software, and hardware, from academia and industry alike. Many important questions need to be addressed, such as what technologies are the most promising candidates for the future, the impact to the software layer such as applications, algorithms compilers and programming models, impact to the architectures such as interconnects, parallelism, and the memory hierarchy, as well as challenges in modeling and simulation of future architectures. However, this list is by no means an exhaustive list of questions.


Paper Format

Papers need to be formatted according to Springer’s single column LNCS style (see this link for LaTeX and Word templates). Papers are limited to 8 pages including figures, references, the abstract, and everything else.


Important Dates

Submission deadline: Friday March 19th 2017, anywhere on earth (AOE).

Notification: Monday April 10th 2017.


Submission Process

Selected papers will be published in ISC’s 2017 workshop proceedings with Springer. Therefore, authors will need to follow instructions on how to release copyright to Springer. By June 10th 2017, authors must provide a conference-ready version of their papers. However, authors will have a chance to revise their papers according to feedback they receive during the workshop and submit a camera-ready version by July 22nd 2017. This is the version that will be published in the proceedings. Instructions will be e-mailed out to the selected papers’s authors.

The review process will be single-blind. This means the identities of the reviewers are not known to the authors, but the identities of the authors are known to the reviewers. Papers may include any number of authors, but there must one author must act as a “contact” author. There is no limit for how many papers a single author or group of authors may submit. At least one author of each selected paper must present the paper during the workshop. We will also collect presentation slides to publish in ISC’s website.


Submission Website

Please submit your paper via Easychair using this link.


List of Topics (Not Exhaustive)

  • Optics and photonics, to include communication, switching, and other emerging topics.
  • Neuromorphic computing. Its current state, as well as future trends for performance and applicable application domains.
  • Quantum computing. Manufacturability, feasibility, application domains, as well as current implementations.
  • Superconducting circuits.
  • Novel device technologies that conform to the digital computing model, such as tunnel FETs, negative capacitance FETs, and carbon nanotube FETs.
  • Novel memory technologies such as resistive RAM, magnetic RAM and other volatile and nonvolatile options.
  • 3D integration. Future capabilities in terms of number of layers, types of layers (memory versus logic), as well as challenges such as heat density.
  • Impact of new technologies to the architecture, to include interconnect, memory hierarchy (such as caches), parallelism, ISA choice, etc.
  • Inexact computing such as approximate computing. What kinds of applications can tolerate errors, and how to use this strategy to mitigate technology problems.
  • Identifying the main application drivers for increased performance.
  • Modelling and evaluation of novel technologies.
  • Software impact of novel technologies, to include programmability, application algorithms, compilation, run-time systems, and other topics.
  • Funding opportunities for research in this field.



Please direct questions to either of the co-chairs: George Michelogiannakis (mihelog at lbl dot gov) or Jeff Vetter (jeff at ornl dot gov).