Workshop on HPC Computing in a Post Moore’s Law World (HCPM) 2017

Welcome to the first workshop of the series on HPC computing in a post Moore’s law world (HCPM)! This workshop will be held on Thursday June 22, 2017 (full day) in conjunction with the 32nd conference of the ISC high performance series, in Frankfurt Germany.

The impending end of traditional MOSFET scaling has sparked research into preserving HPC performance improvements through alternative computational models. To better shape our strategy, we need to understand where each technology is headed and where it will be in a span of 20 years. This workshop brings together experts who develop or use promising technologies to present the state of their work, and spark a discussion on the promise and detriments of each approach. This includes technologies that adhere to the traditional digital computational model, as well as new models such as neuromorphic and quantum computing models.

As part of the workshop, we are accepting paper submissions. Papers will be published in the Springer’s Lecture Notes in Computer Science (LNCS) series. You can find the call for papers with detailed instructions and a link to the submission site here. We will also hold short panels and keynote presentations from experts in the field.

In scope for this workshop are all topics relevant to improving performance for HPC applications after MOSFET scaling (currently driven by Moore’s law) stops:
Optics and photonics, to include communication, switching, and other emerging topics.

  • Neuromorphic computing. Its current state, as well as future trends for performance and applicable application domains.
  • Quantum computing. Manufacturability, feasibility, application domains, as well as current implementations.
  • Superconducting circuits.
  • Novel device technologies that conform to the digital computing model, such as tunnel FETs, negative capacitance FETs, and carbon nanotube FETs.
  • Novel memory technologies such as resistive RAM, magnetic RAM and other volatile and nonvolatile options.
  • 3D integration. Future capabilities in terms of number of layers, types of layers (memory versus logic), as well as challenges such as heat density.
  • Impact of new technologies to the architecture, to include interconnect, memory hierarchy (such as caches), parallelism, ISA choice, etc.
  • Inexact computing such as approximate computing. What kinds of applications can tolerate errors, and how to use this strategy to mitigate technology problems.
  • Identifying the main application drivers for increased performance.
  • Modelling and evaluation of novel technologies.
  • Software impact of novel technologies, to include programmability, application algorithms, compilation, run-time systems, and other topics.
  • Funding opportunities for research in this field.

 

We welcome experts from any field that drives our post Moore’s law future or will be affected by it.

Feel free to contact the co-chairs with any questions, at “mihelog at lbl dot gov” and “vetter at ornl dot gov”.